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High Level Synthesis from C/C++/SystemC to ASIC/FPGA

CyberWorkBench® is C-based High Level Synthesis and Verification tool suite both for ASIC and FPGA.

CyberWorkBench Private demo & presentation @DAC, San Francisco[New]

NEC will exhibit CyberWorkBench® at Design Automation Conference 2018(on Jun. 25-27, 2018 in the U.S.).
Booth number 1437b.
Private presentation & demo.(40 minutes)

Private Demo Reservation Status  Monday, June 25 Tuesday, June 26 Wednesday, June 27
10:00am - 11:00am Available Reserved Reserved
11:00am - 12:00pm Available Reserved Available
12:00pm - 1:00pm Available Available Available
1:00pm - 2:00pm Available Available Available
2:00pm - 3:00pm Reserved Available Reserved
3:00pm - 4:00pm Available Reserved Available
4:00pm - 5:00pm Available Available Available
5:00pm - 6:00pm Available Available Available
 * Please note that takes time to reflect on the reservation table.


Introduction Video

CyberWorkBench® Video

Click the image on the left to watch the product introduction video of CyberWorkBench®.

CyberWorkBench Overview

All the tools listed in Fig. 1 work together in our integrated design environment, for easy synthesis, analysis and verification.

C-based Design Service

We also offer design house services to convert behavioral C descriptions into optimized synthesizable RTL code (Verilog or VHLD) for FPGAs or ASICs.

The advantages of our C-based design house services compared to traditional RTL based services are:
  •Lower cost.
  •Shorted design cycle due to the increase in design productivity of using C as an input language.
  •Generation of higher performance and/or smaller circuits compared to RTL designs because we
    use NEC’s proprietary High-Level Synthesis tool CyberWorkBench®.

Some examples of successful projects include image compression algorithms (JPEG 2000 at 120 fps), image sharpening (e.g. denoising, HDR), encryption systems, communication circuits, CODECs, etc…
Contact us for further information.

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