Generate RTL automatically from ANSI-C language with extensions for hardwares.
Integrated Design Environment（Graphical User Interface)
Integratedly support for synthesis, verification, and analysis in design processes.
Behavior Level Model Generator
Generate a fast simulation model for verification of algorithm in bit-accurate level.
Cycle Level SystemC Model Generator
Generate a fast simulation model in SystemC for verification of algorithm in cycle-accurate and bit-accurate level.
RTL Testbench Generator
Generate a test bench for RTL verification with inputs used in behavioral simulator.
Generate Verilog-HDL/VHDL for logic synthesis.
Code checker for possible overflow in input description.
Bus Interface Generator Standard CPU bus I/F generator (AMBA-AHB/AXI)
Generate behavioral description for standard bus interface (AMBA). AMBA-AHB and AMBA-AXI are supported as an option.
Generate Verilog-HDL/VHDL for logic synthesis. If you need both Verilog-HDL/VHDL, you have to purchase this option.
Generate cycle accurate model from synthesizable Verilog-HDL/VHDL.
Synthesize from SystemC language input.
C Level Property Checker
Verify properties and assertions based on C source.
Generate peripheral circuits and softwares for emulation of circuits synthesized by CWB in LogicBench, which is an FPGA board of Hitachi Information & Communication Engineering, Ltd.
Cycle Level Verilog Model Generator
Generate a fast simulation model in Verilog-VHDL for verification of algorithm in cycle-accurate and bit-accurate level.
Source Code Debugger
A source code debugger capable of cycle level debugging using cycle level Verilog-HDL model.