Video Tutorials
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This video of contributors, is Design Automation and Reconfigurable Computing Laboratory of the Hong Kong Polytechnic University.
This video showcases how to perform formal verification (property checking) in ANSI C code for High Level Synthesis.
Video showing what HLS Design Space Exploration is. The video also shows the difference between
DSE when an ASIC or a FPGA is targeted.
Logic synthesis using Xilinx ISE of the Verilog generated by the HLS tool from the FIR SystemC description