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High speed and compacting electric devices effect increase pin count and processing speed of IC.
This phenomenon requires an IC package to increase pin count and also electric attributes. Therefore, it cause increase cost and longer duration of development.
GENISSNX support to realize cost reduction and shorten development period by the function of IC package automatic layer count estimation and generating net assignment and trace outline.
Provision of the appropriate net assign function between LSI pads and LSI package pins in the development of LSI packages
High speed and large scale of IC have an effect on difficulties and complex for IC package designs.
It takes long to estimate accurate layer count and then it causes loosing business chance. In this case, it might become waste investment for the business.
The package cost is not carefully estimated in order to make a prompt reply, which causes the actual manufacturing cost to rise.
Increased Turn Around Time caused by the package design rule determined at IC planning phase.
Increased turn around time in consideration with electrical characteristics.
Accurate cost estimation for IC package can be shorten.
Overall product image can be shown at IC planning stage.
Period required for examining the possibility of LSI package assembly: 2 weeks > a few minutes.
GENISSNX can perform fast and accurate layer counts estimation.
Trace outline can be generated with short time.
The most appropriate connection relations can be generated between a silicon chip and package pins.
GENISSNX can generate the trace with using the developer's know-how for decreasing the layer counts.
Installation of advanced automatic processing functions such as power source round via integrated processing.
Consideration of electric characteristics such as differential signal and shield interconnection.
Step1：Import or generate initial data
In this time, there are 2 layers.
Generate Trace outline using auto generator function.
As a result, it reveals that 3 layers are needed as a layer for signal traces.
At the same time, it generates initial assignments between chip pad and IC package pin.
Step1：Import or generate initial data manually.
Step2：Generate wire bonding using auto generator function.
At the same time, net assignments between chip pad and finger are generated.
Step3：Generate Trace outline using auto generator function.
At the same time, net assignments between finger and IC package pin are generated, then initial assignments between chip pad and package pin are generated.
