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Our Researchers

February 12, 2020

Hiroaki Inoue

Ph.D.
Senior Manager
Data Science Research Labs

Research area

  • Computer Systems

JOURNAL PUBLICATIONS

  • Sombatsiri, S., Shibata, S., Kobayashi, Y., Inoue, H., Takenaka, T., Hosomi, T., Jaehoon, Y., and Takeuchi, Y. “Parallelism-Flexible Convolution Architecture for Sparse Convolutional Neural Networks on FPGA,” IPSJ Transactions on System LSI Design Methodology (TSLDM), Vol.12, February Issue, pp.22-37 (February 2019). [Best Paper Award]
  • Fukuda, E.S., Inoue, H., Takenaka, T., Kim, D., Sadahisa, T., Asai, T., and Motomura, M., “Enhancing Memcached by Caching Data and Functionalities at Network Interface,” IPSJ Journal of Information Processsing (JIP), Vol.23, No.2, pp.143-152 (March 2015).
  • Denholm, S., Inoue, H., Takenaka, T., Becker, T., and Luk, W. “Network-level FPGA Acceleration of Low Latency Market Data Feed Arbitration,” IEICE Transactions on Information and Systems (Special Section on Reconfigurable Systems), Vol.E98-D, No.2, pp.288-297 (February 2015).
  • Inoue, H., Takenaka, T., and Motomura, M. “C-Based Complex Event Processing on Reconfigurable Hardware,” IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), Vol.21, Issue.5, pp.971-974 (May 2013).
  • Inoue, H., Yamada, J., Yoneda, H., Togawa, K., Motomura, M., and Furuta, K. “Test Compression for Dynamically Reconfigurable Processors,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol.4, No.4, Article 40, pp.1-15 (December 2011) .
  • Inoue, H., Sakai, J., and Edahiro, M. “A Robust Seamless Communication Architecture for Next-Generation Mobile Terminals on Multi-CPU SoCs,” ACM Transactions on Embedded Computing Systems (TECS), Vol.9, No.3, Article 19, pp.1-28 (February 2010).
  • Inoue, H., Abe, T., Ishizaka, K., Sakai, J., and Edahiro, M. “Dynamic Security Domain Scaling on Embedded Symmetric Multiprocessors,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.14, No.2, Article 24, pp.1-23 (March 2009).
  • Inoue, H., Sakai, J., Torii, S., and Edahiro, M. “FIDES: An Advanced Chip Multiprocessor Platform for Secure Next Generation Mobile Terminals,” ACM Transactions on Embedded Computing Systems (TECS), Vol.8, No.1, Article 1, pp.1-16 (December 2008).
  • Inoue, H., Sakai, J., and Edahiro, M. “Processor Virtualization for Secure Mobile Terminals,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.13, No.3, Article 48, pp.1-23 (July 2008). [No.2 downloaded article published in 2008 / No.7 downloaded article published in 1996-2009 (July 2, 2009) / No.2 downloaded article published in 2008 (June 08, 2010)]

CONFERENCE PUBLICATIONS

  • Igarashi, H., Takano, F., Takenaka, T., Inoue, H., and Moriyoshi, T. “Parallel Rate Distortion Optimized Quantization for 4K Real-time GPU-based HEVC Encoder,” IEEE International Conference on Visual Communications and Image Processing (VCIP), pp.1-4 (December 2018).
  • Sombatsiri, S., Shibata, S., Kobayashi, Y., Inoue, H., Takenaka, T., and Hosomi, T. “Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks,” Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp.188-193 (March 2018). [Outstanding Paper Award]
  • Takenaka, T., Inoue, H., Hosomi, T., and Nakamura, Y. “FPGA-Accelerated Complex Event Processing,” IEEE Symposium on VLSI Circuits (VLSIC), pp.C126-C127 (June 2015). [Invited Paper]
  • Fukuda, E.S., Inoue, H., Takenaka, T., Kim, D., Sadahisa, T., Asai, T., and Motomura, M. “Achieving Higher Performance of Memcached by Caching at Network Interface,” IEEE International Conference on Field-Programmable Technology (ICFPT), pp.288-289 (December 2014).
  • Fukuda, E.S., Inoue, H., Takenaka, T., Kim, D., Sadahisa, T., Asai, T., and Motomura, M. “Caching Memcached at Reconfigurable Network Interface,” IEEE International Conference on Field Programmable Logic and Applications (FPL), pp.1-6 (September 2014).
  • Denholm, S., Inoue, H., Takenaka, T., Becker, T., and Luk, W. “Low Latency FPGA Acceleration of Market Data Feed Arbitration,” IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp.36-40 (June 2014).
  • Wakabayashi, K., Takenaka, T., and Inoue, H. “Mapping Complex Algorithm into FPGA with High Level Synthesis,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 282-284 (January 2014). [Invited Paper]
  • Denholm, S., Inoue, H., Takenaka, T., and Luk, W. “Application-Specific Customisation of Market Data Feed Arbitration," IEEE International Conference on Field-Programmable Technology (ICFPT), pp.322-325 (December 2013).
  • Fukuda, E.S., Takenaka, T., Inoue, H., Kawashima, H., Asai, T., and Motomura, M. “High Level Synthesis with Stream Query to C Parser: Eliminating Hardware Development Difficulties for Software Developers,” The Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp.310-315 (October 2013).
  • Fukuda, E.S., Kawashima, H., Inoue, H., Asai, T., and Motomura, M. “Exploiting Hardware Reconfigurability on Window Join,” International Conference on High Performance Computing & Simulation (HPCS), pp.690-691 (July 2013).
  • Fukuda, E.S., Kawashima, H., Inoue, H., Fujii, T., Furuta, K., Asai, T., and Motomura, M. “C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: Window-Join Case Study,” IEEE International Symposium on Applied Reconfigurable Computing (ARC), pp.220 (March 2013).
  • Takagi, M., Takenaka, T., and Inoue, H. “Dynamic Query Switching for Complex Event Processing on FPGAs,” IEEE International Conference on Field Programmable Logic and Applications (FPL), pp.599-602 (August 2012).
  • Takenaka, T., Takagi, M., and Inoue, H. “A Scalable Complex Event Processing Framework For Combination of SQL-based Continuous Queries and C/C++ Functions,” IEEE International Conference on Field Programmable Logic and Applications (FPL), pp.237-242 (August 2012).
  • Inoue, H., Ishizaka, K., and Sakai, J. “Greening of Many-Core Processors in Network-Optimized Computing,” IEEE Global Communications Conference (GLOBECOM), Session SAC08, pp.1-5 (December 2011).
  • Inoue, H., Takenaka, T., and Motomura, M. “20Gbps C-Based Complex Event Processing,” IEEE International Conference on Field Programmable Logic and Applications (FPL), pp.97-102 (September 2011).
  • Koponen, T., Casado, M., Gude, N., Stribling, J., Poutievski, L., Zhu, M., Ramanathan, R., Iwata, Y., Inoue, H., Hama, T., and Shenker, S. “ONIX: A Distributed Control Platform for Large-Scale Production Networks,” USENIX Symposium on Operating Systems Design and Implementation (OSDI), pp.351-364 (October 2010).
  • Inoue, H., Yamada, J., Yoneda, H., Togawa, K., and Furuta, K. “Test Compression for Dynamically Reconfigurable Processors,” IEEE International Conference on Field Programmable Logic and Applications (FPL), pp.205-210 (August 2010).
  • Inoue, H., Li, Y., and Mitra, S. “VAST: Virtualization-Assisted Concurrent Autonomous Self-Test,” IEEE International Test Conference (ITC), Paper 12.3, pp.1-10 (October 2008).
  • Inoue, H., Ikeno, A., Abe, T., Sakai, J., and Edahiro, M. “Dynamic Security Domain Scaling on Symmetric Multiprocessors for Future High-End Embedded Systems,” ACM/IEEE/IFIP International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), pp.39-44 (September 2007). [Best Paper Award]
  • Sakai, J., Inoue, H., and Edahiro, M. “Towards Scalable and Secure Execution Platform for Embedded Systems,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp.350-354 (January 2007). [Invited Paper]
  • Inoue, H., Ikeno, A., Kondo, M., Sakai, J., and Edahiro, M. “VIRTUS: A Processor Virtualization Architecture for Security-Oriented Next-Generation Mobile Terminals,” ACM/IEEE Design Automation Conference (DAC), pp.484-489 (July 2006). [Best Paper Award Nominee]
  • Inoue, H., Ikeno, A., Kondo, M., Sakai, J., and Edahiro, M. “FIDES: An Advanced Chip Multiprocessor Platform for Secure Next Generation Mobile Terminals,” ACM/IEEE/IFIP International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), pp.178-183 (September 2005).
  • Sakai, J., Inoue, H., Abe, T., Suzuki, N., Uekubo, M., Ito, Y., Suzuki, K., Kondo, M., and Edahiro, M. “Multi-Tasking Parallel Method on MP211 Application Processor,” IEEE International Symposium on Low-Power and High-Speed Circuits (COOL Chips), pp.198-211 (April 2005).
  • Matsushita, S., Torii, S., Nomura, M., Inoue, T., Shibayama, A., Shimada, S., Ohsawa, T., Inoue, H., Sakai, J., Ito, Y., Nakamura, Y., Edahiro, M., Nishi, N., and Yamashina, M. “Merlot: A Single-Chip Tightly Coupled Four-Way Multi-Thread Processor,” IEEE International Symposium on Low-Power and High-Speed Circuits (COOL Chips), pp.63-74 (April 2000).
  • Nishi, N., Inoue, T., Nomura, M., Matsushita, S., Torii, S., Shibayama, A., Sakai, J., Ohsawa, T., Nakamura, Y., Shimada, S., Ito, Y., Edahiro, M., Mizuno, M., Minami, K., Matsuo, O., Inoue, H., Manabe, T., Yamazaki, T., Nakazawa, Y., Hirota, Y., Yamada, Y., Onoda, N., Kobinata, H., Ikeda, M., Kazama, K., Ono, A., Horiuchi, T., Motomura, M., Yamashina, M., and Fukuma, M. “A 1GIPS 1W Single-Chip Tightly-Coupled Four-Way Multiprocessor With Architecture Support for Multiple Control Flow Execution,” IEEE International Solid-State Circuits Conference (ISSCC), pp.418-419 (February 2000).
  • Inoue, H., Anjo, K., Tanabe, J., Nishimura, K., Satoh, M., Hiraki, K., and Amano, H. “MBP-light: A Processor for Management of Distributed Shared Memory on JUMP-1,” International Symposium on Low-Power and High-Speed Circuits (COOL Chips), pp.169-182 (April 1999).
  • Inoue, H., Anjo, K., Yamamoto, J., Tanabe, J., Wakabayashi, M., Satoh, M., Amano, H., and Hiraki, K. “The Preliminary Evaluation of MBP-light with Two Protocol Policies for a Massively Parallel Processor - JUMP-1 -,” IEEE Symposium on the Frontiers of Massively Parallel Computation (FRONTIERS), pp.268-275 (February 1999).
  • Inoue, H., Anjo, K., Tanabe, J., Nishimura, K., Satoh, M., Hiraki, K., and Amano, H. “MBP-light: A Processor for Management of Distributed Shared Memory,” International Conference on ASIC (ASICON), pp.199-202 (October 1998).

POSTER

  • Igarashi, H., Takano, F., Inoue, H., and Moriyoshi, T. “4K Real-Time CUDA-Based HEVC Encoder,” GPU Technology Conference (GTC), (March 2018).

MAGAZINES

  • Sakai, J., Inoue, H., Torii, S., and Edahiro, M. “Multitasking Parallel Method for High-End Embedded Appliances,” IEEE Micro, Vol.28, No.5, pp.54-62 (September/October 2008).
  • Inoue, H., and Sato, N. “FIDES: A Multi-Core Platform to Enhance Robustness of Embedded Systems,” NEC Technical Journal, Vol.1, No.3, pp.51-54 (July 2006).
  • Torii, S., Sakai, J., Inoue, H., Tokue, T., and Ito, Y. “Asymmetric Multi-Processing Mobile Application Processor MP211,” NEC Journal of Advanced Technology, Vol.2, No.3, pp.204-210 (Summer 2005).

BOOKS

  • Inoue, H., Takenaka, T., and Motomura, M. “Hardware Design for C-Based Complex Event Processing,” in Athanas, P., Pnevmatikatos, D., and Sklavos, N. “Embedded Systems Design with FPGAs,” Springer Verlag, ISBN: 978-1461413615, Chapter 4, pp.79-100 (December 2012).

HONORS AND AWARDS

  • The Best Paper Award for IPSJ Transactions on System LSI Design Methodology (TSLDM) 2019 (August 2019)
  • An outstanding paper award for Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2018 (March 2018).
  • Top 2 downloaded article published in 2008 for ACM Transactions on Design Automation of Electronic Systems (June 2010).
  • Top 2 downloaded article published in 2008, and Top 7 downloaded article published in 1996-2009 for ACM Transactions on Design Automation of Electronic Systems (July 2009).
  • The best paper award for ACM/IEEE/IFIP International Conference on Hardware/Software Co-design and System Synthesis (September 2007).
  • A best paper award nominee for ACM/IEEE Design Automation Conference (July 2006).

Academic/professional career summary

March 1999
Master of Engineering, Keio University
April 1999
Central Research Laboratories, NEC
October 2007
Visiting Scholar, Stanford University (until September 2008)
September 2009
Ph.D., Keio University
April 2014
Corporate Technology Division, NEC
October 2015
IoT Strategy Office, NEC
April 2017
Central Research Laboratories, NEC

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