GENISSNX® WB Function/FC Function
IC Package Layer Count Estimation and Virtual Design Tool
Overview of GENISSNX® WB Function/FC Function
High-speed and compact electric devices increase pin count and processing speed of IC.
This phenomenon requires an IC package to increase its pin count and electric attributes, thereby increasing costs and lengthening development time.
GENISSNX helps reduce costs and shorten the development period by the IC package automatic layer count estimation function and by generating net assignment and trace outline.
- Provision of the appropriate net assign function between LSI pads and LSI package pins in the development of LSI packages.
High-speed and large-scale ICs make it difficult and complex to design IC packages.
Problem of cost estimation in business negotiations
It takes a long time to accurately estimate the layer count, which can cause the loss of a business opportunity. In this case, it might mean a wasted investment for the business.
The package cost might not be carefully estimated in order to make a prompt reply, which could cause the actual manufacturing cost to rise.
Improved price estimates in business negotiations regarding the acceptance of LSI development.
Time taken for accurate cost estimation for IC package can be shortened.
- Overall product image can be shown at IC planning stage.
Reduce turnaround time for design with automatic processing in consideration of package restrictions and electrical characteristics.
- Period required for examining the possibility of LSI package assembly: 2 weeks > a few minutes.
GENISSNX can perform fast and accurate layer count estimation.
- Trace outline can be generated within a short time.
- The most appropriate connection relations can be generated between a silicon chip and package pins.
GENISSNX can generate the trace while using the developer's know-how to decrease the layer counts.
- Installation of advanced automatic processing functions such as power source round via integrated processing.
- Consideration of electric characteristics such as differential signal and shield interconnection.
Trace Outline Generated by GENISSNX FC Function
- Step 1：Import or generate initial data
At this time, there are two layers.
- Step 2 : Generate trace outline using auto generator function
Result shows that three layers are needed as layers for signal traces.
At the same time, it generates initial assignments between chip pad and IC package pin.
Trace Outline Generated by GENISSNX WB Function
- Step 1：Import or generate initial data manually
- Step 2：Generate wire bonding using auto generator function
At the same time, net assignments between chip pad and finger are generated.
Step 3：Generate trace outline using auto generator function
At the same time, net assignments between finger and IC package pin are generated, followed by initial assignments between chip pad and package pin.