IC Package Design Support Tool
GENISSNX helps ensure efficient processing at the IC package design phase. This product has ERC (Electrical Rule Check) function (GENISSNX ERC Function) to check if there are electrical problems in the routed design data. It also has a high-speed, high-accuracy layer count estimator including an outline trace generator （GENISSNX WB Function/FC Function） that enables the provision of optimized connection information within IC packages on the basis of auto-routing technology.
The ERC (Electric Rule Check) function detects problems with electric characteristics caused by the IC package. The resultant report from the ERC function considers electric characteristics such as EMI or associated design information that requires attention, thus supporting the development of a high-quality IC package.
This is a world-first tool that auto-computes the layer count of an IC package (FCBGA) and optimizes the connectability between chip pads and package pins. It offers comprehensive support for IC package design flow in IC development.
Contents of provision/Contents of composition
- GENISSNX ERC Function (Electrical Rule Check for IC Package)
- GENISSNX WB Function (Layer Count Estimation for PBGA type IC Package)
- GENISSNX FC Function(Layer Count Estimation for FCBGA type IC Package)
These functions are available for single or combination use
- CAD (APD) link option from CADENCE
Glossary of terms
- TAT: Turn Around Time
- LSIPKG: LSI Package
- FCBGA: Flip Chip Ball Grid Array
- SiP: System in Package