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GENISSNX®IC Package Design Support Tool
GENISSNX allows you to promote efficiency process at IC package design phase. This product has ERC Function (Electrical Rule Check) function (GENISSNX ERC Function) to check if there are electrical problems in the routed design data, and high speed and accuracy layer count estimator including outline trace generator （GENISSNX WB Function/FC Function） which enable to provide optimized connection information within IC package based on auto-routing technology.
ERC Function (Electric Rule Check) function detects electric characteristics problems caused by IC package. Reporting ERC Function result considered electric characteristics like EMI or associated design information needed to pay attention electrically supports your high quality IC package development.
World's first tool that auto-computes the layer count of IC package (FCBGA), and optimum connectability between chip pads and packages pins. Comprehensive support for IC package design flow in IC development.
Contents of provision/Contents of conmposition
- GENISSNX
- GENISSNX ERC Function (Electrical Rule Check for IC Package)
- GENISSNX WB Function (Layer Count Estimation for PBGA type IC Package)
- GENISSNX FC Function(Layer Count Estimation for FCBGA type IC Package)
These functions are available for single or combination use
- CAD (APD) link option from CADENCE
Glossary of terms
- TAT: Turn Around Time
- LSIPKG: LSI Package
- FCBGA: Flip Chip Ball Grid Array
- SiP: System in Package
