ESD and PI Options
ESD Rule Check
A discharge can occur when an electrically charged object (including the human body) touches an electronic device. This phenomenon called ESD (Electrostatic discharge) causes malfunction and failure of electronic devices.
EMIStream ESD Rule Check Feature will detect areas where ESD tolerance levels are low on a PCB and offer suggestions for solutions.
Check rules and threshold values are based on real-world cases from companies around the globe and are verified through research at NEC Lab.
Possible ESD problems are detected at an early design stage, thus decreasing time spent on evaluation processes.
Import the CAD layout data, complete a simple set-up, and you are ready to run ESD Rule Check.
Factors causing ESD are instantaneously pointed out, enabling you to take immediate action to solve the problems.
10 Rule Check Items
ESD Rule Check Feature includes Signal Trace, Component Placement Validity, and FG Pattern Check Groups consisting of ten key check rules.
Signal Trace Check Group
- Traces Near Plane Edge
- Traces crossing over power and ground plane
- Signal trace over the slit of the ground/power plane (*1)
- SG Trace
- SG Via Spacing
- Power Protection
- (*1) Signal trace over the slit of the ground/power plane
If a signal trace is crossing over the slit of the ground/power plane, it causes ESD noise on signals. This check will detect such structural problems and displays a warning message.
Component Placement Validity Check Group
- Input Pin Protection
- Power Pin Protection
- Reset Line Protection (*2)
- (*2) Reset Line Protection
- Even though noise suppression components (such as capacitors) are added to the ESD sensitive signal trace or power source, they cannot effectively reduce ESD noise if they have not been properly placed. This check points out if the location of the component is not ideal and shows a warning message.
FG Pattern Check Group
- FG Pattern
- The ESD noise flows into signal traces and power/ground planes if an FG pattern has an inadequate signal width or inappropriate via positions crossing over the layers.
In addition, the distance between the FG pattern and power/ground planes will affect the noise flow. This check analyzes the FG pattern structure and its distance from power/ground planes and displays a warning message if there are any problems.
Power Integrity Analysis
The Power Integrity Analysis Function will help you analyze the location and value of capacitors in order to prevent IC from malfunctioning. Using this function, you can optimize capacitors by taking both EMI and PI into account.
This will help you meet target impedance by adding/moving capacitors and changing capacitance values, plane shapes, and power/ground plane distances.
IC Model Generation GUI
You can now take the capacitance and inductance of the chip and package into account by using the GUI. These values affect mid frequency resonance which is an important aspect for power integrity. By utilizing this function you can get a more accurate result in order to optimize capacitor placement, values, and numbers.