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Event
Exhibition
| DesignCon 2013 | |
|---|---|
| Date | January 29-30, 2013 |
| Venue | Santa Clara Convention Cener, CA, USA |
| NEC Booth No. | 316 |
| Country or Area | USA |
| Event Type | Conference / Exhibition |
| URL | The official website |
Seminar
| Date | February 1, 2013 (FRI) |
|---|---|
| Schedule | 9:30 AM to 10:00 AM Registration 10:00 AM to 10:15 AM TechDream Introduction 10:15 AM to 11:00 AM “ESD Simulator Verification – Techniques and Current Requirements” 11:00 AM to 12:00 PM “Suppressing EMI and Mitigating ESD at Early Design Stage” 12:00 PM to 1:00 PM Lunch break (buffet lunch provided) 1:00 PM to 2:30 PM “Avoiding PCB level ESD – Tips on ESD Free Design” |
| Venue | Ramada Inn Silicon Valley 1217 Wildwood Avenue Sunnyvale, CA 94089 |
| Country | US |
| Contents | Mr. Doug Smith will cover ESD design issues for circuit boards and how to avoid problems. Data will be presented to illustrate design approaches. Videos will also be used to show experiments and data to support suggested design approaches. Case histories and war stories will be included. This will be a high energy, high intensity talk! |
| Details and Registration | View Seminar Details and Pre-Registration *Official Seminar website |
